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Parallel Architecture for High Throughput JPEG2000 Block Decoder
Betreuer M.Eng. Trung Hieu Tran
Prüfer Prof. Dr.-Ing. Sven Simon
EndeJun. 2019

Data Compression plays a crucial roles in a wide variety of applications. One of important applications is image compression in which high compression ratios in companion with acceptable quality loss is always expected, as images are used in every modern software application. Up to now, JPEG2000 is still considered as the most effective compression standard for still image. However, JPEG2000 relies on EBCOT (Embedded Block Coding with Optimized Truncation) which was known to be high computation complexity. This complexity limits the use of JPEG2000 in real-time applications and also make it less preferable for hardware realization. Recently, there are many alternative to EBCOT are proposed with intention to offer a large reduction in complexity while accepting a small reduction in compression efficiency.

Goals of this thesis: In this master thesis an efficient parallel architecture for block decoding algorithm will be developed and implemented on FPGA (Field-programmable Gate Array) platform. FPGA is a widely used platform for image processing application because of its high capability of parallelism and reconfiguration. The proposed architecture are first prototyped with Simulink System Generator. Several test pictures will be used for objective comparison with JPEG2000/EBCOT encoder. The final FPGA implementation will be compared with related works on both processing throughput and hardware resource consumption. The duration of the thesis will be 6 months (full-time).


  • Knowledge of VHDL
  • Knowledge of Matlab is an advance


Trung Hieu Tran (trung.hieu.tran@ipvs.uni-stuttgart.de)

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