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Accelerators for CT reconstruction on Intel Heterogeneous architecture with FPGA

This thesis is a part of the Intel Hardware Accelerator Research Program (Intel HARP: https: //software.intel.com/en-us/hardware-accelerator-research-program) and is aimed at designing hardware architecture for accelerators for computed tomography (CT) reconstruction. The Intel HARP program is based a heterogeneous architecture with an Intel Xeon processor and an Intel Arria 10 FPGA integrated in a single package. This architecture provides a unique capability to provide accelerations for computation intensive algorithm which in our case are the 3D CT reconstruction algorithm. The primary goal of this thesis is to design and implement accelerators for the CT reconstruction algorithm. CT is a 3D measuring technique where an object is scanned with X-ray from various directions and then this information is fed to a computation intensive reconstruction algorithm to obtain a 3D model of the object. The increasing pixel resolution in CT (e.g. using a 4Kx4K x-ray detector)
leads to volume data sets of up to 256 GBytes and requires numerous hours of computation times for CT reconstruction even on high performance multicore CPU. Therefore, hardware acceleration is used as a standard technique for decreasing the computation time.
• Competence in C is required in this thesis.
• Competence in VHDL / Verilog is required in this thesis.
• Prior knowledge in CT reconstruction algorithm is not necessary.
Feel free to contact me if you have any further questions. For applying for this thesis please send us your latest transcript of marks and a short resume.